a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device with a metal silicide film formed on the surface of an active region of a semiconductor substrate and its manufacture method.
b) Description of the Related Art
In order to achieve high performance of semiconductor devices, it is effective to reduce the resistance and contact resistance of impurity doped regions and gate electrodes. As a method of reducing these resistances, a method (a salicide film forming method) is known which forms a metal silicide film in a self-alignment manner on the upper surface of a gate electrode and the surfaces of source/drain regions on both sides of the gate electrode. The metal silicide films reduce the resistance and contact resistance of the gate electrode and source/drain regions.
The salicide film forming method will be described briefly. Side spacer insulating films are formed on the side walls of a gate electrode. The side spacer insulating films electrically separate the surfaces of source/drain regions from the upper and side walls of the gate electrode. A metal film capable of silicification reaction is deposited covering the gate electrode and source/drain regions. The substrate is heated to silicidize the metal film with silicon. A metal silicide film is therefore formed on the upper surface of the gate electrode and the surfaces of the source/drain regions in a self-alignment manner.
In order to improve the data storage characteristics of a memory cell of a semiconductor device such as a dynamic random access memory (DRAM), it is desired to reduce junction leak current of an impurity doped region. However, if a metal silicide film is formed on the surface of an impurity doped region, the junction leak current increases (refer to the 178-th Meeting the Electro-chemical Society, pp. 218-220). From this reason, in DRAM manufacture, the salicide film forming method is not used in general.
If DRAM cells and logic circuits are formed on the same substrate and the salicide film forming method is not used, the resistances of gate electrodes, source/drain regions and the like of MOSFET""s constituting logic circuits become high. It is therefore difficult to improve the performance of logic circuits. In order to improve the performance of logic circuits without shortening a storage time of DRAM cells, it is desired to apply the salicide film forming method only to MOSFET""s of logic circuits.
It is an object of the present invention to provide a semiconductor device in which only desired regions among a plurality of active regions on the surface of a semiconductor substrate is silicidized, and its manufacture method.
According to one aspect of the present invention, there is provided a semiconductor device comprising: a semiconductor substrate having a principal surface defined with first and second regions; two projected patterns disposed spaced apart from each other by a certain distance and formed on the principal surface in the first region, the two projected patterns running on a first active and on an element isolation region around the first active region in the first region; a first metal silicide film formed on a surface of an active region in the principal surface in the second region; and a burying member for covering side walls of the two projected patterns and burying a space between the two projected patterns at least in the element isolation region, the burying member being not formed above the two projected patterns, wherein a metal silicide film is not formed on a surface of the first active region.
The resistance of a surface layer of the active region with the first metal sulicide film can be lowered. In the active region without the metal silicide film, junction leak current of the impurity dopes regions can be reduced.
According to another aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate having a principal surface defined with first and second regions; first and second gate electrodes disposed spaced apart from each other by a certain distance and formed on the principal surface in the first region, the first and second gate electrode running on a first active region in the first region; a MOSPET formed in the second region; a first metal silicide film formed on surfaces of source/drain regions of the MOSFET; a second metal silicide film formed on upper surfaces of the first and second gate electrodes; a third metal silicide film formed on an upper surface of a gate electrode of the MOSFET; a first insulating member formed on the second metal silicide; a second insulating member covering side walls of the first and second gate electrodes and side walls of the first insulating member; and a third insulating member covering the source/drain regions of the MOSFET and the third metal silicide film and made of a same material as the first insulating member, an upper surface of the third insulating member being swelled upward in correspondence to the gate electrode of the MOSFET, wherein a metal silicide film is not formed on a surface of the first active region.
In the active region with the first metal silicide film, the resistance of the surface layer can be lowered. In the active region without the metal silicide film, junction leak current of the impurity dopes regions can be reduced. The upper surfaces and side walls of the first and second gate electrodes are covered with the first and second insulating members. If a contact hole is formed through an interlayer insulating film formed above the first and second gate electrodes under the conditions that the first and second insulating members are not etched, these first and second insulating members protect the first and second gate electrodes. The contact hole can therefore be formed in a self-alignment manner.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of; preparing a semiconductor substrate having a principal surface defined with first and second active regions; forming first and second gate electrodes above the first active region of the semiconductor substrate, the first and second gate electrodes being made of silicon and spaced apart by a certain distance, and forming a third gate electrode made of silicon above the second active region; depositing an insulating film over the principal surface, the insulating film covering the first to third gate electrodes; anisotropically etching the insulating film to leave a portion of the insulating film so as to completely fill a space between the first and second gate electrodes and leave a portion of the insulating film on side walls of the third gate electrode, to thereby expose a surface of the second active region outside of the insulating film covering the side walls of the third gate electrode and expose upper surfaces of the first to third gate electrodes; and forming a metal silicide film on a surface of the exposed second active region and on the upper surfaces of the first to third gate electrodes.
A space between the first and second gate electrodes is filled with a portion of the insulating film. Since the silicon substrate surface is not exposed in the space therebetween, the metal silicide film will not be formed in this area.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: a deposition step of depositing a silicon film on a surface of a silicon substrate having a principal surface; a patterning step of patterning the silicon film to leave the silicon film in a first region of the principal surface and leave a first gate electrode made of the silicon film in an active region of a second region; a side spacer forming step of forming side spacer insulating members covering side walls of the first gate electrode; a first ion doping step of doping impurity ions into active regions on both side the first gate electrode; a metal silicide forming step of forming a metal silicide film on surfaces of the active regions outside of the side spacer insulating members, on an upper surface of the first gate electrode, and on a surface of the silicon film left in the first region; a second gate electrode forming step of patterning the silicon film and the metal silicide film formed thereon both left in the first region to leave a second gate electrode above the active region in the first region; and a second ion doping step of doping impurity ions into active regions on both sides of the second gate electrode.
During the metal silicide forming step, the silicon film is left in the first region. Therefore, the silicon surface in the first region is not subject to a silicification reaction. Only the surface of the active region in the second region can be subject to the silicification reaction.
As above, a metal silicide film is formed on the silicon surface in some area of the semiconductor substrate, and it is not formed in the other area. If this structure is applied to DRAM with logic circuits, a metal silicide film is formed on the surfaces of the source/drain regions of MOSFET""s of the logic circuit area, and it is not formed on the surfaces of the source/drain regions in the memory cell array area. In the logic circuit area, the metal silicide film lowers the resistance of the source/drain regions of MOSFET to thereby improve the device performance. In the memory cell array area, the metal silicide film is not formed so that it is possible to prevent the storage time from being shortened.